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XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
SFR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)
? Logic 0 = Enable Receiver (default).
? Logic 1 = Disable Receiver.
SFR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)
For the 9-bit mode information, See ”Section 1.17, Normal Multidrop (9-bit) Mode - Receiver” on page 23.
? Logic 0 = Normal 8-bit mode (default).
? Logic 1 = Enable 9-bit or Multidrop mode.
SFR[7]: TX Address Bit (Requires EFR[4] = 1)
This bit requires that forced "0" parity is enabled (LCR[5:3]=’111’). If this bit is enabled, the 9th bit of the next
byte written to THR will be a ’1’. This bit resets after a write to THR. For the 9-bit mode information, See
? Logic 0 = Value of 9th bit will be ’0’ (default).
? Logic 1 = Value of 9th bit will be ’1’.
3.12
Scratch Pad Register (SPR) - Read/Write
This is an 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
3.13
GPIO Level Register (GPIOLVL) - Read/Write
This register provides the current state of the GPIO pins.
If a GPIO has been configured as an input:
■
■
A read will report the current state of the input.
A write to any GPIO configured as an input will not have any effect.
If a GPIO has been configured as an output:
■
■
A read will report the current value of the register. The current value of the register will also be the
current state of the output pin if three-state mode is not enabled (GPIO3T register).
A write will change the current value of the register. The current value of the register will also be the
current state of the output pin if three-state mode is not enabled (GPIO3T register).
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